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IS23SC4418/4428 integrated silicon solution, inc. 1-800-379-4774 1 advance information nv001-0c 02/05/99 issi ? this document contains advance information data. issi reserves the right to make changes to its products at any time without no tice in order to improve design and supply the best possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 1999, integrated silico n solution, inc. IS23SC4418 is23sc4428 1-kbyte eeprom with write protect function and programmable security code (psc) advance information february 1999 features ? standard cmos process ? 1024 x 8 bits eeprom organization ? byte-wise addressing ? byte-wise erase/write ? irreversible byte-wise write protection ? single 5v power supply for read and write/erase ? low power operation: C 3 ma typical active current ? 5 ms programming time ? 3-wire serial interface ? 20 khz serial clock rate ? contact configuration and serial interface, iso standard 7816 (synchronous transmission) compatible. ? high esd protection: > 4 kv ? high reliability: C 1,000,000 erase/write cycles guaranteed C 10 years data retention ? wide operating temperature range C 0 to +70 c commercial; C40 to +85 c industrial additional feature of is23sc4428: ? 2-byte programmable security code (psc) for memory write/erase protection description IS23SC4418 IS23SC4418 contains 1024 x 8 bits of eeprom with programmable write protection for each byte. random read access to any byte in the memory is always possible. the memory can also be erased and written byte by byte. erasing old data in the byte location must be performed before new data can be written to the location. each byte in the memory has a corresponding protect bit. the protect bits are only one-time programmable and cannot be erased. after the protect bits are enabled (logic 0), the corresponding bytes can never be changed again. a write-protect bit with data-compare function is available for user to verify the data in the memory before enabling the protect bit. is23sc4428 is23sc4428 offers all the features in IS23SC4418. in addition, it offers two bytes of programmable security code (psc) against unauthorized memory write/erase operations. all the memory, except for the psc can always be read, but the memory can be written or erased only after psc verification. if the user fails to enter the correct psc in eight consecutive attempts, the device will block any further psc entry attempts and the memory can never be erased or written again. the psc bytes are pre-programmed by the manufacturer with a code, which is specified for the customer for device transport security purposes, before the devices are shipped to the customer. the error counter will be pre-erased by the manufacturer to allow maximum attempts (maximum of eight) for psc entry. issi ?
IS23SC4418/4428 2 integrated silicon solution, inc. 1-800-379-4774 advance information nv001-0c 02/05/99 issi ? gnd i/o clk reset, blockade logic high-voltage generator, substate-current generator sense amp and comparator 1024 x 8 eeprom with decoder 1024 protect bits (otp) programming control sequencer and security logic interface rst vcc figure 1. block diagram
IS23SC4418/4428 integrated silicon solution, inc. 1-800-379-4774 3 advance information nv001-0c 02/05/99 issi ? pin names pin card contact symbol description 1 c1 vcc supply voltage 2 c2 rst reset 3 c3 clk serial clock 4 c4 nc no connect 5 c5 gnd ground 6 c6 nc no connect 7 c7 i/o serial data i/o (open drain) 8 c8 nc no connect c1 c2 c3 c4 c5 c6 c7 c8 vcc rst clk nc gnd nc i/o nc pin descriptions symbol type card contact name and function vcc c1 supply voltage rst c2 reset: the device reset pin (rst) is used to take the device out of the power-on reset state (por). when the operating power is first applied to vcc, the device goes into por state. the por state can be terminated by rst in this sequence: bring rst from 0 to 1 and then change clk from 0 to 1 (see figure 4). this reset operation terminates any active command operation. after the por state has been terminated, a read operation must be performed before any data can be erased or written. also, IS23SC4418/28 meets the iso 7816 specification on answer to reset function. the answer to reset can be invoked by performing the following steps: 1) rst goes from 0 to 1; 2) clk pulse is applied; 3) rst changes from 1 to 0. if these steps are performed correctly, the device will set the address counter to 0 and the first data bit at byte address 0 will appear on the output (i/o). by continuing to send pulses at clk, the contents of the following byte addresses can be read out of the device. (see figure 3) in normal operation, rst controls the data input and output directions. when sending data/command to the device, rst is set to 1. when reading data/psc verification output from the device, rst is set to 0. (see figure 4) clk c3 serial clock: this is the device data clock pin. it is used to clock data bits into and out of the device. nc c4, c6, c8 no connect gnd c5 ground i/o c7 serial data input and output: this pin is where data is shifted in and out of the device. figure 2. pin configuration
IS23SC4418/4428 4 integrated silicon solution, inc. 1-800-379-4774 advance information nv001-0c 02/05/99 issi ? vcc bit1 bit2 bit31 bit32 32 2 1 rst t are t rsts1 t rsth t d t dh t h clk i/o t l figure 3. reset and answer to reset timing diagram figure 4. general timing for data input, data output and psc verification data input data output or psc verification rst clk bit0 01 t re t ds t dh 23 bit1 bit23 bit0 01 23 bit1 bit2 i/o t h t rsth t rsts2 t d t l
IS23SC4418/4428 integrated silicon solution, inc. 1-800-379-4774 5 advance information nv001-0c 02/05/99 issi ? table 1. control words for IS23SC4418/4428 commands command name byte 1 byte 2 byte 3 s0 s1 s2 s3 s4 s5 a8 a9 a0-a7 d0-d7 read 8-bits data without protect bit 011100 a8 a9 a0-a7 don't care read 9-bits data with protect bit 001100 a8 a9 a0-a7 don't care write and erase without protect bit (1) 110011 a8 a9 a0-a7 input data write and erase with protect bit (1) 100011 a8 a9 a0-a7 input data write protect bit with data comparison (1) 000011 a8 a9 a0-a7 com pare data additional commands for is23sc4428 only (3) write error counter 010011 11 fdh bit mask verify first psc byte 101100 11 feh psc byte 1 verify second psc byte 101100 11 ffh psc byte 2 write and erase first psc byte 110011 11 feh psc byte 1 without protect bit (2) write and erase second psc byte 110011 11 ffh psc byte 2 without protect bit (2) write and erase first psc byte 100011 11 feh psc byte 1 with protect bit (2) write and erase second psc byte 100011 11 ffh psc byte 2 with protect bit (2) read 8-bits first psc byte 011100 11 feh don't care without protect bit (2) read 8-bits second psc byte 011100 11 ffh don't care without protect bit read 9-bits first psc byte 001100 11 feh don't care with protect bit read 9-bits second psc byte 001100 11 ffh don't care with protect bit notes: 1. if the protect bit of the byte address is enabled, the write command will have no effect on the byte content. 2. if the protect bit of the psc byte is enabled, the write command will have no effect on the psc byte. 3. for is23sc4428, locations (1021-1023) are occupied by error counter and psc codes and thus cannot be used for general data storage.
IS23SC4418/4428 6 integrated silicon solution, inc. 1-800-379-4774 advance information nv001-0c 02/05/99 issi ? rst i/o clk command address data s0 s1 s2 s3 s4 s5 a8 a9 a0 a1 a2 a3 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 d6 d7 0123456 7 0123456 7 0123456 7 general command descriptions read 8-bits data the read 8-bit data command allows the user to specify the address (a0-a9) of the data byte to be read from the device. the byte address for the next output data is automatically incremented after every eight clock pulses. the data is output in sequential order, with the data from address n followed by the data from address n+1. (see figure 6.) read 9-bits data with protect bit the read 9-bit data command operates similarly to read 8- bit data command except that the protect bit for each byte is output after each 8-bit data and the address for the next output data is incremented after every nine clock pulses. (see figure 7.) write/erase data byte without protect bit the write/erase data byte without protect bit command writes the new data into the specified byte location. there are three kinds of write/erase operations which are automatically executed by the device: 1. erase and subsequent write if 203 clock pulses at f < 20 khz are applied. (see figure 8.) 2. write only if 103 clock pulses at f < 20 khz are applied. this operation is only suitable if single bits of one byte shall be changed only from 1 to 0. (see figure 9.) 3. erase only if the input data = ffh and 103 clock pulses at f < 20 khz are applied. (see figure 9.) note : erase means 0 ? 1. write means 1 ? 0. if the protect bit of the corresponding byte location is enabled, the write/erase operation will have no effect on the content. write/erase data byte with protect bit the write/erase data byte with protect bit command operates similarly to the write/erase data bytewith protect bit command except that it also writes 0 to the corresponding protect bit. after the protect bit is set to 0 (write protection enabled), it cannot be changed again. (see figures 8 and 9.) write protect bit with data comparison the write protect bit with data comparison command writes 0 to the corresponding protect bit only if the input data and the data in the specified memory location are the same. after the protect bit is set to 0 (write protection enabled), it cannot be changed again. (see figure 9.) the execution of write/erase commands are terminated after a given number of clock cycles. when the operation is done, the device will bring the i/o state to 0. only rst transition from 0 to 1 can set the i/o state back to 1. figure 5. command entry sequence
IS23SC4418/4428 integrated silicon solution, inc. 1-800-379-4774 7 advance information nv001-0c 02/05/99 issi ? rst address start address (a0-a9) start address + n start address + 1 to start address + (n-1) i/o clk command entry data output 0 s0 xx xx d7 23 0 1 2 3 4 56701 0 1 234567 d0 d1 d2 d3 d4 d5 d6 d7 d0 d0 d1 d2 d3 d4 d5 d6 d7 xxx rst address start address (a0 - a9) start address + n start address + 1 to start address + (n-1) i/o clk command entry data output 0 s0 xx xx d7 23 0 1 2 3 4 56780 0 1 234567 8 d0 d1 d2 d3 d4 d5 d6 d7 p8 d0 d1 d2 d3 d4 d5 d6 d7 p8 xxx figure 6. read 8-bit data figure 7. read 9-bit data with protect bit x - don't care p8 - '0' if the protect bit is enabled. - '1' if the protect bit is disabled.
IS23SC4418/4428 8 integrated silicon solution, inc. 1-800-379-4774 advance information nv001-0c 02/05/99 issi ? rst i/o clk e/w (internal signal) command entry programming erase t e write 0 s0 d6 23 0 1 2 99 102 103 199 202 d7 s1 t w rst i/o clk e/w (internal signal) command entry programming erase only or write only 0 s0 d6 23 0 1 2 89 102 d7 s1 figure 8. programming erase and write figure 9. programming erase only or write only
IS23SC4418/4428 integrated silicon solution, inc. 1-800-379-4774 9 advance information nv001-0c 02/05/99 issi ? is23sc4428 security features overview without entering programmable security code (psc), only memory read access is possible. however, the content of the psc addresses (1022 and 1023) cannot be read out. if reading psc is attempted, 00h will be output. the psc verification procedure must be performed in the following sequence: 1. write one to not-written error counter bit, address 1021 2. enter first psc byte, address 1022 3. enter second psc byte, address 1023 4. after successful psc verification, the error counter should be erased to reactivate the 8 psc entry attempts. if the psc entry is incorrect, go back to step 1. if all the error counter bits have been written, any further psc entry will be blocked and trhe memory can never be changed again. writing error counter the number of erased bits (logic 1) in error counter determines the number of possible attempts (maximum of eight). before psc entry, only writing of error counter is possible. after psc is successfully verified, the counter can now be erased. before disconnecting the supply voltage vcc, the counter should be erased in order to reactivate the eight attempts. (see figure 10.) entry of psc the least significant psc byte beginning with the least significant bit must be entered first and then the most significant (see table 1). if both psc byte 1's and byte 2's comparisons prove correct, the memory erase/write access will be enabled and psc may be changed as wished, except the corresponding protect bits are 0 (enabled). (see figure 11.) condition when supplied is23sc4428 is supplied by the manufacturer with a 2-byte psc (transport security code) which is determined in cooperation with the customer. rst i/o clk e/w (internal signal) command entry writing error counter write 0 s0 d6 23 0 1 2 89 102 d7 s1 figure 10. writing error counter
IS23SC4418/4428 10 integrated silicon solution, inc. 1-800-379-4774 advance information nv001-0c 02/05/99 issi ? absolute maximum ratings symbol parameter min. max. unit vcc supply voltage C0.3 6 v vi input voltage C0.3 6 v t stg storage temperature C40 125 c p max power dissipation 60 mv capacitance (t a = 25 c, v cc = 5.0v 10%, f = 1 mh z ) symbol parameter conditions max. unit c in input capacitance v in = 0v 5 pf c out output capacitance v out = 0v 8 pf rst i/o clk command command entry verification in progress address a0 = 0 for psc byte 1 a0 = 1 for psc byte 2 psc byte 1 or byte 2 psc byte verification finished 0 101 10 01 1a0 11111 11 d0 d1 d2 d3 d4 d5 d6 d7 123456 7 0123456 7 0123456 701 figure 11. psc verification
IS23SC4418/4428 integrated silicon solution, inc. 1-800-379-4774 11 advance information nv001-0c 02/05/99 issi ? dc characteristics (t a = 0 to 70 c, v cc = 5.0v 10%, gnd = 0v) symbol parameter test conditions min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v i cc supply current 3 10 ma v ih input high voltage (i/o, clk, rst) 3.5 5.0 v v il input low voltage (i/o, clk, rst) 0 0.8 v i ih input high current (i/o, clk, rst) 10 m a i ol output low current v ol = 0.4v, open drian 0.5 ma i oh output high leakage current v oh = 5v, open drian 10 m a ac characteristics (t a = 0 to 70 c, v cc = 5.0v 10%, gnd = 0v) symbol parameter test conditions min. typ. max. unit f c clock frequency 20 khz t re reset time 9 m s t a re answer to reset 20 50 m s t h clock high period 10 m s t l clock low period 10 m s t w write time (fc = 20 khz) 5 ms t e erase time (fc = 20 khz) 5 ms t rsts 1 reset setup time 1 4 m s t rsts 2 reset setup time 2 4 m s t rsth reset hold time 4 m s t ds write data setup time 4 m s t dh write data hold time 4 m s t d read data delay time 6 m s t r rise time (i/o, clk, rst) 1 m s t f fall time (i/o, clk, rst) 1 m s
IS23SC4418/4428 12 integrated silicon solution, inc. 1-800-379-4774 advance information nv001-0c 02/05/99 issi ? issi ? integrated silicon solution, inc. 2231 lawson lane santa clara, ca 95054 tel: 1-800-379-4774 fax: (408) 588-0806 e-mail: sales@issi.com www.issi.com ordering information commercial range: 0 c to +70 c order part number package is23sc4428-x2 sorted wafer is23sc4428-x3 dice in waffle pack after backgrinding to 8-9 mil. is23sc4428-x4 dice in waffle pack after backgrinding to 10-11 mil. is23sc4428-x5 sorted wafers on a ring is23sc4428-x6 individual modules is23sc4428-x7 taped modules is23sc4428-x8 blank cards industrial range: C40 c to +85 c order part number package is23sc4428-x2i sorted wafer is23sc4428-x3i dice in waffle pack after backgrinding to 8-9 mil. is23sc4428-x4i dice in waffle pack after backgrinding to 10-11 mil. is23sc4428-x5i sorted wafers on a ring is23sc4428-x6i individual modules is23sc4428-x7i taped modules

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